AVX 512 on a Dedicated Server: Which Workloads Actually Gain

An AVX 512 server can apply one instruction to 512 bits of data at once, twice the width of AVX2. Every EPYC server in our range, Zen 4 and Zen 4c alike, supports AVX 512, while our Xeon E5 v3 and v4 servers support AVX2 only. It speeds up vectorised number crunching such as inference, encoding and hashing, not ordinary web serving.

AVX2 vs AVX 512: what the wider vectors change

SIMD instructions apply one operation to every element in a register. An AVX2 register holds 256 bits, which is 8 single precision floats or 32 bytes. An AVX 512 register holds 512 bits, which is 16 floats or 64 bytes, so the same data needs half as many instructions when the code is built to use them.

AVX 512 also doubles the vector registers from 16 to 32, adds mask registers so loops with conditions vectorise cleanly, and brings new instructions for low precision dot products and cryptography that have no AVX2 equivalent.

Our Xeon E5 v3 (Haswell EP) and E5 v4 (Broadwell EP) chips have AVX2 with FMA, the fused multiply add most numerical code relies on, but none of these extras.

How Zen 4 runs AVX 512

AMD added AVX 512 with Zen 4, the core inside the EPYC 9254 and EPYC 9554. Zen 4 keeps full 512 bit registers but executes most 512 bit instructions on its 256 bit wide datapaths in two passes. That design avoids the large clock drops some earlier Intel server chips showed under heavy AVX 512 load, which slowed down everything else sharing those cores.

Two passes do not cancel the benefit, because fewer instructions to decode, more registers, masking and the new instructions all still help. The EPYC 9754 uses Zen 4c cores with the same instruction set, AVX 512 included, but a smaller cache per core and lower clocks.

The Zen 4 extensions worth knowing

• VNNI multiplies 8 bit integers and adds the results into 32 bit totals in one instruction, a job that takes three instructions with AVX2. Quantised inference runs on exactly that operation.
• BF16 handles bfloat16, a 16 bit floating point format, with dot products that accumulate in 32 bit precision.
• VAES runs AES rounds on several blocks per instruction across a full vector register.
• VPCLMULQDQ is a vector carry less multiply, used for the GHASH step of AES GCM and for fast CRC checksums.

Workloads that gain from AVX 512

The common thread is the same arithmetic repeated over long arrays of numbers or bytes, with few branches and the data already in memory.

AVX 512 for LLM inference on CPU

llama.cpp and similar runtimes spend most of their time multiplying matrices of quantised weights, which is what VNNI and BF16 accelerate. Prompt processing, where the model reads your input, is compute bound and gains the most. Token generation is usually limited by memory bandwidth, because each new token reads most of the model's weights from RAM. The EPYC 9004 platform has twelve DDR5 memory channels per socket, and bandwidth depends on how many are populated. See our guide to AI and machine learning workloads and our earlier article on running a language model on CPU.

Other workloads that gain

• Video encoding and decoding. Blocks of pixels go through identical steps, so SVT AV1 and dav1d include hand written AVX 512 code for inner loops such as filters and transforms, selected at run time when the build includes it. See our transcoding and media processing guide.
• Compression and hashing. BLAKE3 and xxHash ship AVX 512 implementations, and CRC routines fold many bytes per instruction with VPCLMULQDQ. Compression gains less evenly, because the parts that follow data dependent branches do not vectorise.
• JSON parsing. simdjson classifies a whole block of input bytes at once and picks its AVX 512 kernel at run time on CPUs that support it, Zen 4 included.
• Analytical databases. Column stores with vectorised execution, such as ClickHouse, run filters and aggregations over batches of values from one column, the shape wide vectors suit best.
• Numerical Python. NumPy and SciPy hand matrix work to an optimised BLAS library such as OpenBLAS, which uses AVX 512 kernels when it detects support, with no change to your Python code.
• Bulk encryption. Recent OpenSSL releases use VAES and VPCLMULQDQ to speed up AES GCM, which pays off on busy TLS proxies and VPN gateways.

Workloads that gain little

If your server spends its time waiting, wider vectors do not help:

• PHP and typical web apps. WordPress and Laravel run interpreted, branch heavy code and wait on the database. Clock speed and cache matter far more, as our web hosting and WordPress guide explains.
• I/O bound services such as file servers, mail servers and backup jobs, limited by disk and network throughput.
• Most databases doing point lookups. Fetching one row by primary key is index walking, locks and memory latency. Our database server guide covers what matters there.
• Anything waiting on network or disk, from API gateways to queue workers calling external services.

For these, the AVX2 Xeons do the job at a lower price per core.

Your software has to use AVX 512

A CPU flag does nothing on its own. Either software is compiled for AVX 512, by giving GCC or Clang the target name znver4 or the option that targets whatever machine you build on, or it dispatches at run time, choosing the best code path it carries for the CPU it finds. simdjson, OpenSSL, OpenBLAS and the video codecs above dispatch, so one binary runs on both our Xeons and our EPYCs.

The trap is software built for the generic 64 bit x86 baseline with no dispatch. Many distribution packages and container images are compiled for that baseline so one build runs everywhere, and unless the code dispatches at run time it never touches AVX 512, even on Zen 4. A container sees the host CPU directly, so what counts is how the binary inside was built. For llama.cpp, the simplest fix is to build it on the server itself, because its default build targets the CPU it is compiled on.

How to check AVX 512 on Linux

Run lscpu and read the Flags line, or search /proc/cpuinfo. Look for avx512f, the AVX 512 foundation, then avx512_vnni for the 8 bit dot products used in quantised inference and avx512_bf16 for bfloat16. The EPYC 9254, 9554 and 9754 report all three. The Xeon E5 chips report avx2 and no avx512f. The flags only prove the CPU can do it. To confirm the software side, llama.cpp prints the instruction set features it was built with when it starts.

Which of our servers support AVX 512

Prices are monthly in euros and include the 1 Gbps unmetered port.

Server	Core generation	Vector instructions	VNNI and BF16	Cores / threads	Price per month
Dual Xeon E5 2630 v3	Haswell EP	AVX2	No	16 / 32	€225
Dual Xeon E5 2690 v4	Broadwell EP	AVX2	No	28 / 56	€249
Dual Xeon E5 2699 v4	Broadwell EP	AVX2	No	44 / 88	€325
Single EPYC 9254	Zen 4 (Genoa)	AVX 512	Yes	24 / 48	€485
Dual EPYC 9254	Zen 4 (Genoa)	AVX 512	Yes	48 / 96	€739
Dual EPYC 9554	Zen 4 (Genoa)	AVX 512	Yes	128 / 256	€1049
Dual EPYC 9754	Zen 4c (Bergamo)	AVX 512	Yes	256 / 512	€1659

AVX 512 dedicated server: which one to pick

• Start with the Single EPYC 9254 at €485 a month. 24 cores at up to 4.15 GHz, 128 GB of DDR5 and one socket, so no NUMA tuning.
• Move to the Dual EPYC 9554 at €1049 for heavy parallel inference or encoding, with 128 cores and 512 GB of DDR5. Keep each inference process on one socket, as explained in single vs dual socket servers and NUMA.
• Choose the Dual EPYC 9754 at €1659 for maximum throughput per euro on parallel batch work. Its 256 cores and 1 TB of DDR5 come to €6.48 per core per month, the lowest in our range. Its slower cores with less cache suit many independent jobs, as covered in EPYC 9554 vs 9754: Genoa or Bergamo.

If your work is not vectorised, the AVX2 Xeons stay the value pick. The Dual Xeon E5 2699 v4 gives you 44 cores for €325 a month, €3.69 per thread, and our dedicated server cost per core comparison shows where each server lands.

Questions we get

Does EPYC support AVX 512?

EPYC supports AVX 512 from Zen 4 onwards, which means the 9004 series, Genoa and Bergamo included. The earlier 7001, 7002 and 7003 series stop at AVX2. Every EPYC we sell is a 9004 series part.

Will software built for AVX2 run on the EPYC servers?

Yes. Zen 4 and Zen 4c support AVX2 as well, so anything that runs on our Xeon E5 servers runs unchanged. It just will not use 512 bit instructions until it is rebuilt or dispatches at run time.

Do I need AVX 512 to run llama.cpp?

No. llama.cpp has AVX2 code paths and runs on the Xeon E5 servers. AVX 512 with VNNI and BF16 speeds up the compute heavy parts, and how much depends on the model, quantisation, thread count and memory bandwidth, so test with your own model.

Can virtual machines on the server use AVX 512?

Yes, if the hypervisor passes the flags through. In Proxmox VE the default CPU type for new VMs is a generic model without AVX 512, so set the CPU type to host for VMs that need it and check lscpu inside the guest.

Next step: pick your AVX 512 server

If your workload is inference, encoding, hashing or analytics, start on an EPYC and check your build on day one. The EPYC servers are built to order with delivery in about 14 days, the Xeons deliver in about 45 minutes, and there is no setup fee. Compare all seven on our dedicated servers page.